Title:
【考案の名称】メモリ装置
Document Type and Number:
Japanese Patent JP2517123
Kind Code:
Y2
Abstract:
An improved memory organization for use in a computer display system including a display having a plurality of display pixels for defining images that includes: a frame buffer memory having a plurality of memory cells organized into a matrix, said memory comprising first and second maps wherein the contents of the maps correspond to the pixels and define characteristics of the pixels, the maps being defined along X and Z axes of the matric; reading means coupled to the frame buffer memory for selectively reading, in one memory cycle operation, a plurality of bits from memory cells defining one of the maps; writing means coupled to said frame buffer memory for selectively storing, in one memory cycle operation, a plurality of bits into memory cells defining one of the maps; control logic means coupled to the reading means and the writing means for generating control signals for selectively reading a plurality of bits from one of the maps and writing a plurality of bits into one of the maps to define the images to be displayed on said display; wherein multiple maps may be defined in an array of memory cells, each of the maps providing different characteristics for the pixels of the display.
Inventors:
Peter W Costello
Application Number:
JP1195995U
Publication Date:
November 13, 1996
Filing Date:
October 16, 1995
Export Citation:
Assignee:
Sun Microsystems,Inc.
International Classes:
G06F12/06; G06T1/60; G09G5/02; G06F12/00; G09G5/39; G09G5/36; G09G5/395; (IPC1-7): G06T1/60; G06F12/06; G09G5/36
Domestic Patent References:
| JP6076790A | ||||
| JP61296385A | ||||
| JP52126A |
Attorney, Agent or Firm:
Masaki Yamakawa (2 outside)