Title:
【発明の名称】LRUエラ-処理方式
Document Type and Number:
Japanese Patent JP2541528
Kind Code:
B2
Abstract:
PURPOSE:To obtain a processing system without deterioration in performance and increase of a hardware quantity, by deciding one memory block to be replaced by an LRU system, and generating a random number considering a cache allocation prohibiting level and a cache non-mounting level when the abnormality of an instruction is detected, and selecting whether or not it is the output of a random number circuit. CONSTITUTION:An abnormality detecting means, when one memory block to be replaced by the cache memory device of set associative system being decided and designated, detects the abnormality of indication. The random number circuit 19, when the abnormality is detected, decides a designated replacing block based on the random number generated considering the cache allocation prohibiting level and the cache non-mounting level. And a selection means 18 selects the indication or the output of the random number circuit 19 corresponding to the output of the abnormality detecting means 16, and when the abnormality is recognized by the abnormality detecting means 16, the output of the random number circuit 19 is outputted as an object for the replacement of the cache.
Inventors:
AONO FUMIO
Application Number:
JP31036786A
Publication Date:
October 09, 1996
Filing Date:
December 26, 1986
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F12/12; G06F12/16; (IPC1-7): G06F12/12; G06F12/16
Domestic Patent References:
| JP5845682A | ||||
| JP60176156A | ||||
| JP53109441A | ||||
| JP4962047A | ||||
| JP477506A | ||||
| JP5835641A | ||||
| JP568426B2 |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)