Title:
【発明の名称】ダイナミックRAM
Document Type and Number:
Japanese Patent JP2542706
Kind Code:
B2
Abstract:
A semiconductor memory device is disclosed which comprises a regular row/column memory cell array (22a to 22d) having blocks obtained by dividing the memory cell array in the column and row directions, a first peripheral circuit (23) irregularly provided between the blocks divided in the column direction; a second peripheral circuit (24a, 24c) provided between the blocks divided in the row direction and including a first decoder, a third peripheral circuit (25) provided between the first peripheral circuit and the respective block and including a second decoder; and a fourth peripheral circuit (29) provided at the marginal portion of the memory cell array and including bonding pads and input protection circuit.
Inventors:
FUJII HIDETAKE
SHIMIZU MITSURU
SHIMIZU MITSURU
Application Number:
JP26087189A
Publication Date:
October 09, 1996
Filing Date:
October 05, 1989
Export Citation:
Assignee:
TOSHIBA KK
TOSHIBA MAIKUROEREKUTORONIKUSU KK
TOSHIBA MAIKUROEREKUTORONIKUSU KK
International Classes:
G11C11/41; G11C5/02; G11C8/12; G11C11/401; G11C11/407; H01L27/10; (IPC1-7): H01L27/10
Domestic Patent References:
| JP3214669A |
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)