Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2543870
Kind Code:
B2
Abstract:
PURPOSE:To shorten the total time required by turning off all transfer gates at the time of refresh, detaching a pair of split bit lines from a main bit line, selecting one word line at every split bit line and refreshing it by a sense amplifier. CONSTITUTION:Split bit lines DBL(DBL11-DBLmn), the inverse of DBL(the inverse of DBL11- the inverse of DBLmn) to which a memory M(M111-Mmn2) of a one capacity and one transistor has been connected is connected to main bit lines BL(BL1-BLm), the inverse of BL(the inverse of BL1-BLm) through a transfer gate T(T111-Tmn1). On the main and split bit lines, sense amplifiers BS(BS1-BSm), DBS(DBS11-DBSmn) are provided, word lines WL(WL11-WLn2) of the same number as pairs of split bit lines by a signal DS, its DBS is activated by a signal F(F1-Fn), and the cell is refreshed by one piece at every time. At the time of selecting the word line WL, the gates T are all turned off and the split bit line is detached from the main bit line, and the cell of one piece is refreshed by the pair of split bit lines. At the time of readout/write, a pair of gates T are turned on, and only one pair of split lines are connected to one main bit line. According to this constitution, the time required for refresh decreases remarkably with regard to all the word lines.
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Inventors:
SAKUI YASUSHI
WATANABE SHIGENOBU
WATANABE SHIGENOBU
Application Number:
JP4697587A
Publication Date:
October 16, 1996
Filing Date:
March 02, 1987
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G11C11/401; G11C7/18; G11C11/34; G11C11/406; G11C11/4097; (IPC1-7): G11C11/401; G11C11/406
Domestic Patent References:
| JP5919291A | ||||
| JP6142794A | ||||
| JP581890A | ||||
| JP58139392A | ||||
| JP6326897A |
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)