Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP2544826
Kind Code:
B2
Abstract:
A semiconductor integrated circuit has an output circuit which includes a Bi-CMOS circuit of receiving an input signal, and an ECL circuit. The ECL circuit includes a differential pair for receiving an output of the Bi-CMOS circuit, na an emitter follower for receiving an output of the differentail pair. The Bi-CMOS circuit comprises a CMOS inverter connected in series between power sources; a first npn transistor, a diode, and a second npn transistor which are connected in series between the power sources; and second and third n-channel MOS transistors for turning the second npn transistor ON and OFF. This semiconductor integrated circuit provides a stable, operation and low power consumption.
Inventors:
SATO SHINZO
SHIMAUCHI YUKI
SHIMAUCHI YUKI
Application Number:
JP12752390A
Publication Date:
October 16, 1996
Filing Date:
May 17, 1990
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H03K19/0175; H03K19/0944; (IPC1-7): H03K19/0175
Attorney, Agent or Firm:
Fumihiro Hasegawa