Title:
【発明の名称】半導体デバイスの製造方法
Document Type and Number:
Japanese Patent JP2546745
Kind Code:
B2
Abstract:
A semiconductor device of the MOS construction such that a gate oxide film of the device has a gate area in the range of from 5 to 15 mm<2> and a thickness in the range of from 15 to 40 nm and the oxide film dielectric breakdown voltage is not less than 8 MV/cm when a gate current caused to flow in response to application of a direct-current voltage between a phosphorus-doped polysilicon electrode formed on the oxide film and a silicon single crystal substrate increases past 1 mu A/mm<2> as current density is obtained by using a silicon wafer substrate having an oxygen concentration of not more than 1 x 10<1><8> atoms/cm<3>.
Inventors:
FUSEGAWA IZUMI
YAMAGISHI HIROTOSHI
FUJIMAKI NOBUYOSHI
KARASAWA YUKIO
YAMAGISHI HIROTOSHI
FUJIMAKI NOBUYOSHI
KARASAWA YUKIO
Application Number:
JP7687591A
Publication Date:
October 23, 1996
Filing Date:
March 15, 1991
Export Citation:
Assignee:
SHINETSU HANDOTAI KK
International Classes:
H01L21/02; H01L21/28; H01L21/322; H01L29/78; (IPC1-7): H01L29/78; H01L21/02
Domestic Patent References:
| JP613415A | ||||
| JP59101863A |
Attorney, Agent or Firm:
Koichi Tateno