Title:
【発明の名称】通信制御装置
Document Type and Number:
Japanese Patent JP2546901
Kind Code:
B2
Abstract:
PURPOSE:To obtain the communication controller of simple constitution, which fits for high speed transmission by using the independent accessibility of respective ports of a dual port memory. CONSTITUTION:A protocol processing processor 3 receives a transmission request from high-order CPU 2, and accesses to a dual port memory for transmission data 4 through a contention control circuit 7, whereby it adds header information and the like to transmission data in accordance with a protocol. A DMA control circuit 6a is transmission-started. The control circuit 6a executes the DMA operation of a serial port access and outputs transmission data from the serial port of the memory 4. The transmission data is converted into serial data based on the control signal of the DMA control circuit 6a in a transmission control circuit 9. Then, data is transmitted to a transmission line. Thus, transmission data can be stored into the dual port memory of high-order CPU 2 without the prevention of the access. Consequently, transmission can be speeded up.
Inventors:
OGURA TOSHIHIKO
IKEDA NAOYA
KATSUBE TAKEKI
IKEDA NAOYA
KATSUBE TAKEKI
Application Number:
JP31598789A
Publication Date:
October 23, 1996
Filing Date:
December 05, 1989
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F13/00; H04L29/02; (IPC1-7): H04L29/02
Domestic Patent References:
| JP6412356A | ||||
| JP62501454A |
Attorney, Agent or Firm:
Kazuko Tomita