Title:
【発明の名称】薄膜トランジスタ・アレイ装置
Document Type and Number:
Japanese Patent JP2559773
Kind Code:
B2
Abstract:
An array of thin film transistor (TFT) devices is provided with a conductive region, such as a strip, for temporarily coupling a floating pel electrode of each of the plurality of TFT devices to a conductor on an underlying substrate. The conductor may be a row or column metalization line associated with an adjacent row or column of the array. The conductive strip may therefore be utilized, in conjunction with appropriate voltage potentials and test circuitry, to test each of the TFT devices prior to the final fabrication of the TFT array into a completed flat panel display. Thus, nonfunctioning or out of specification arrays may be identified at an early point in the manufacturing cycle of the display. The strip may be comprised of amorphous silicon which is illuminated during the test in order to reduce the intrinsic resistance of the strip. The strip may also be comprised of a layer of metalization, which layer is removed from the array at the completion of the test.
Inventors:
HOORU MATSUSHU ARUTO
Application Number:
JP28229087A
Publication Date:
December 04, 1996
Filing Date:
November 10, 1987
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G01R31/265; G02F1/13; G02F1/136; G02F1/1368; G09G3/00; G09G3/36; H01L21/336; H01L21/66; H01L21/768; H01L23/58; H01L27/12; H01L29/78; H01L29/786; G02F1/1362; (IPC1-7): G02F1/136; G09G3/36; H01L29/786
Domestic Patent References:
| JP61170724A |
Attorney, Agent or Firm:
Kiyoshi Goda (3 others)