Title:
【発明の名称】信号周期計測装置
Document Type and Number:
Japanese Patent JP2563366
Kind Code:
B2
Abstract:
PURPOSE:To attain measurement with finer accuracy than the limit of an operating speed of a counter by combining the rough measurement by the counter and the minute measurement using a delay time of a logic gate for the measurement of the signal period. CONSTITUTION:An analog signal F whose amplitude is limited and the 1st clock C1 are given to a D flip-flop 4 to output the 1st control signal P1. The signals F, P1 are given to a pulse width detection circuit 10 to detect a pulse with W shorter than the signal C1. The signals F, P1 and inverted clocks C1, C2 are given to a logic circuit 5 to obtain a control signal P2. The signal C1, P2 are given to a counter 6 and its output is given to a latch 7 together with the signal P2 to obtain a high-order digit as the output 12. The signals W, P2 are given to a latch 8, the output WA is given to a latch 9 together with the signal P2 to obtain the signal WB. The signals WA, WB are subtracted to obtain a low-order digit as the output. Thus, the delay time of the logic circuit is used to attain minute measurement more than the limit of the counter operating speed.
Inventors:
HAYASHI KATSUHIKO
Application Number:
JP22072987A
Publication Date:
December 11, 1996
Filing Date:
September 03, 1987
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K3/64; G01R23/10; (IPC1-7): H03K3/64
Domestic Patent References:
| JP59155766A | ||||
| JP60111971A |
Attorney, Agent or Firm:
Tomoyuki Takimoto