Title:
【発明の名称】ダイナミツク型フリツプフロツプ
Document Type and Number:
Japanese Patent JP2564300
Kind Code:
B2
Abstract:
PURPOSE:To obtain a FF capable of being set/reset by constituting the FF by a clocked inverter inverting an input signal synchronously with the 1st clock pulse and a clocked logic gate receiving the output signal and other signal to synchronize the 2nd clock. CONSTITUTION:A terminal 1 receiving a signal Din, a clocked inverter 10 receiving a clock pulse phi, a clocked NOR gate 20 receiving an output 7 and a reset signal 8 and receiving an inverse of phi, and a terminal 2 from which an output Dout is given are connected in series to form a dynamic FF. Through the constitution above, an inverse of Din 7 from the inverter 10 is given to a gate of PMOS 21, MMOS 25 being components of a NOR gate 20, then the inverter 10 and the NOR gate 20 are operated by an inverted clock, and the output signal Dout keeps a prescribed level when the pulse phi is at a high level and a reset signal 8 is given to the NOR gate 20 when the pulse phi goes to a low level.
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Inventors:
SHINOSAWA MEGUMI
NAKAGAKI NOBUFUMI
HARADA HIROSHI
KUBOTA SADAO
NAKAGAKI NOBUFUMI
HARADA HIROSHI
KUBOTA SADAO
Application Number:
JP8880887A
Publication Date:
December 18, 1996
Filing Date:
April 13, 1987
Export Citation:
Assignee:
HITACHI LTD
International Classes:
H03K3/356; H03K3/037; (IPC1-7): H03K3/037; H03K3/356
Domestic Patent References:
| JP55104121A | ||||
| JP5636219A | ||||
| JP50138763A | ||||
| JP6087521A | ||||
| JP61154216A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)