Title:
【発明の名称】可変速度受信機
Document Type and Number:
Japanese Patent JP2583138
Kind Code:
B2
Abstract:
A variable data rate receiver is provided which employs a novel phase locked loop (PLL) of the type employing a data detection loop and a tracking loop. The data detection loop is initially not coupled to the input of the voltage controlled oscillator in the tracking loop of the PLL, but is separated by an electronic switch. A phase lock detection circuit is provided which is coupled to the data detection loop and to the tracking loop for detecting the difference in the voltage error signals in the data detection loop and the tracking loop. When this error signal indicates that the tracking loop is locked on to the carrier signal the electronic switch is closed completing the phase locked loop circuit after lock on of the carrier is achieved.
Inventors:
KIITO KURISUTOFUAA REIMONDO
ARUBANASU GUREN AASAA
ARUBANASU GUREN AASAA
Application Number:
JP50142889A
Publication Date:
February 19, 1997
Filing Date:
December 16, 1988
Export Citation:
Assignee:
UNISYS CORP
International Classes:
H04L27/227; (IPC1-7): H04L27/227
Domestic Patent References:
| JP6162449U |
Attorney, Agent or Firm:
Fukami Hisaro (2 outside)