Title:
【発明の名称】発振制御回路
Document Type and Number:
Japanese Patent JP2585147
Kind Code:
B2
Abstract:
PURPOSE:To prevent the oscillation from being disturbed due to the effect of noise caused at a post-stage circuit LA by devising the control circuit such that the post-stage circuit LA is in operation after an amplitude of an oscillation signal reaches a prescribed value or over. CONSTITUTION:An oscillating potential of an oscillation signal stays between an inverting potential (2.0V) of a CMOS inverter IV1 and an inverting potential (3.0V) of a CMOS inverter IV2 at a small amplitude for the oscillation initial period. Thus, the logical output of the inverters IV1, IV2 is respectively '0' and '1' and a logical output of an inverter IV4 is '1'. Thus, the CMOS inverter comprising MOS transistors(TRs) T12, T13 is kept inoperative till the oscillating signal exceeds any inverting potential.
Inventors:
AOYANAGI FUMITAKA
HASEGAWA EIICHI
HASEGAWA EIICHI
Application Number:
JP5673791A
Publication Date:
February 26, 1997
Filing Date:
March 20, 1991
Export Citation:
Assignee:
NIPPON PURESHIJON SAAKITSUTSU KK
International Classes:
H03B5/32; G06F1/04; H03K3/02; H03K12/00; (IPC1-7): H03B5/32; H03K3/02; H03K12/00
Domestic Patent References:
| JP2228106A | ||||
| JP2277303A |
Attorney, Agent or Firm:
Kazuko Matsuda