Title:
【発明の名称】半導体メモリセルおよびその製造方法
Document Type and Number:
Japanese Patent JP2586182
Kind Code:
B2
Abstract:
In a semiconductor memory cell of a DRAM comprising a stacked cell capacitor (310a,310b) constructed upon word and bit lines (304a,304b,304c,314a,314b) the stacked cell capacitor is not directly connected to a transistor. A local wiring from the diffusion layer of the transistor to the device isolator area is provided. Through this wiring, the diffusion layer of the transistor is connected to the stacked cell capacitor (310a,310b). Also, a bit line is contructed on the active region to cross the connection point between the transistor, local wiring and gate electrode.
Inventors:
TERADA KAZUO
Application Number:
JP13314690A
Publication Date:
February 26, 1997
Filing Date:
May 23, 1990
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/108; H01L21/8242
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)