Title:
【発明の名称】半導体メモリ装置
Document Type and Number:
Japanese Patent JP2591314
Kind Code:
B2
Abstract:
Out of a plurality of digit lines consisting of first layer aluminum wirings that are connected respectively to a plurality of memory cells forming a memory cell array region, and sense amplifiers that have the digit lines selected by Y selector circuits as the inputs are arranged in the direction of the digit lines of the memory cell array region. At least a part of the wirings between the plurality of the digit lines and the sense amplifiers are disposed as second layer aluminum wirings on the memory cell array region. By so arranging it is possible to provide sophisticated sense amplifiers in a semiconductor memory device which has a large number of output bits and yet a high speed operation is required for it.
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Inventors:
NARAHARA TETSUYA
Application Number:
JP27827690A
Publication Date:
March 19, 1997
Filing Date:
October 17, 1990
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C5/02; G11C7/06; G11C17/12; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/10; H01L27/10
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)