Title:
【発明の名称】メモリ装置
Document Type and Number:
Japanese Patent JP2596208
Kind Code:
B2
Abstract:
A memory apparatus includes a memory cell array for storing a data, a shift register for receiving an input serial data to be stored in the memory cell array and supplying an output serial data to be read from the memory cell array, and a transfer gate for transferring a data in parallel between the shift register and the memory cell array. In the shift register, the input serial data is shifted to an output side thereof until the first bit reaches to the final step thereof. Then, the input serial data is transferred to be stored in the memory cell array by the transfer gate. Thus, when the stored data is read therefrom, no invalid bit is supplied even at the beginning time even if the shift register is longer than the input serial data.
Inventors:
Hoshino Yasuyo
Application Number:
JP28282690A
Publication Date:
April 02, 1997
Filing Date:
October 19, 1990
Export Citation:
Assignee:
NEC
International Classes:
G11C7/00; G11C7/10; G11C11/401; G11C29/00; G11C29/04; (IPC1-7): G11C7/00; G11C29/00
Domestic Patent References:
| JP545656A | ||||
| JP4121890A | ||||
| JP246590A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)