Title:
【発明の名称】パルスによって消去可能なEPROM
Document Type and Number:
Japanese Patent JP2596903
Kind Code:
B2
Abstract:
EPROM memory comprising an array of memory cells consisting of MOS transistors (1) with floating gate (2). Certain memory cells have been electrically programmed with the result that electrons are trapped on the floating gate of the corresponding MOS transistors. The drain (3), the source (4) and the channel (8) of a memory cell to be erased, being joined together, there is applied to them a series of voltage gating pulses of positive amplitude relative to the control gate with the result that the trapped electrons acquire energy enabling them to leave the floating gate (2) for the substrate (5). The cell is thus erased. Application to EPROM memories.
Inventors:
Philip Kargy
Application Number:
JP14923088A
Publication Date:
April 02, 1997
Filing Date:
June 16, 1988
Export Citation:
Assignee:
SGS-Thomson Microelectronics S
International Classes:
G11C17/00; G11C16/04; G11C16/14; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; G11C16/02; G11C16/04; G11C16/06; H01L29/788; H01L29/792
Domestic Patent References:
| JP58118094A | ||||
| JP5630767A |
Attorney, Agent or Firm:
Takashi Koshiba