Title:
【発明の名称】メモリアドレス制御装置
Document Type and Number:
Japanese Patent JP2609629
Kind Code:
B2
Abstract:
PURPOSE: To attain address control by hardware, to speed up address calculation and to reduce the load of a CPU by providing the memory address controller with two address data generation means for successively specifying respective addresses of a picture memory. CONSTITUTION: The controller executes the address control of a normal display mode, a PIP display mode, an enlarged display mode, and a multi-picture display mode based upon data set up in latch circuits 18, 20, 26, 28 and control data CD1 to CD4 outputted from a control circuit 29. The controller for executing the address control is provided with counters 12, 14 for generating the horizontal address data of the picture memory 11, counters 13, 15 for generating the vertical address data of the memory 11, data subtracting circuits 17, 19, count value selecting circuits 21, 22, shift circuits 23, 24 for changing the inclinations of selected outputs, and data adders 25, 27 and respective control functions can be driven only by setting up data from a CPU 16.
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Inventors:
Noriya Sakamoto
Application Number:
JP23676587A
Publication Date:
May 14, 1997
Filing Date:
September 21, 1987
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H04N11/00; G06F3/153; G06T1/60; G06T3/40; G09G1/00; G09G1/02; G09G5/00; G09G5/14; G09G5/36; G09G5/39; H04N11/24; (IPC1-7): G09G5/36; G06T3/40; G09G5/14; G09G5/36
Domestic Patent References:
| JP61285488A | ||||
| JP6226034B2 |
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)