Title:
【発明の名称】電気接続体の形成方法
Document Type and Number:
Japanese Patent JP2618460
Kind Code:
B2
Abstract:
In making electrical connections (4A,34A and 4B,34B) to a substructure (10) of a VLSI or other integrated circuit, a first conductive material (4) e.g. W is blanket deposited over an insulating layer (1) and in sub-micron openings (2) and is then etched away though a thickness sufficient to remove it from the upper surface (3) of the insulating layer (1) while leaving it as plugs (4A,4B) in the openings (2). Due to various processing inhomogeneities, the structure (Figure 3) produced by this etching step may have large step-downs of e.g. 0.6 mu m depth in at least some sub-micron openings (2). This can cause step-coverage problems for the next layer of material (34A,34B), e.g. Al. These problems can be avoided in accordance with the invention by first etching the insulating layer (1) in such manner as to form a new upper surface (9) at a level lower than or substantially the same as the upper surfaces of the plugs (4A,4B). This etching which produces step-ups rather than step-downs at the openings 2 is preferably performed after depositing a sacrificial planarizing layer (7) on the insulating layer (1).
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Inventors:
Rainier de Weld
Reindelt de Bruin
Reindelt de Bruin
Application Number:
JP30108288A
Publication Date:
June 11, 1997
Filing Date:
November 30, 1988
Export Citation:
Assignee:
Philips Electronics Nemrose Fennaught Shap
International Classes:
H01L21/3205; H01L21/768; (IPC1-7): H01L21/3205
Domestic Patent References:
| JP61112353A | ||||
| JP61283145A | ||||
| JP6232630A | ||||
| JP6243175A | ||||
| JP5591843A | ||||
| JP62114447U |
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)