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Title:
【発明の名称】ディジタル式位相比較回路
Document Type and Number:
Japanese Patent JP2619448
Kind Code:
B2
Abstract:
A digital phase comparing circuit includes: first and second input terminals (IN1, IN2); a level change detecting circuit (D1, D2) for detecting changes in levels of first and second input signals (S1, S2) applied to the first and second input terminals, respectively, and outputting first and second detection signals (S3, S4) indicating the changes in levels; and a flip-flop circuit (FF3, FF4, 11) which is set in response to an input of one of the first and second detection signals and which is reset in response to a following input of one of the first and second detection signals. The digital phase comparing circuit outputs a pair of output signals (S5, S6; S7, S8) having a pulse width corresponding to a phase difference ( phi , phi 1, phi 2) between the first and second input signals, thereby making it convenient for a following circuit to utilize both "H" level and "L" level signals, while simplifying the process and facilitating the high degree of integration thereof.

Inventors:
Tokushi Hidetaka
Application Number:
JP32532287A
Publication Date:
June 11, 1997
Filing Date:
December 24, 1987
Export Citation:
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Assignee:
富士通株式会社
International Classes:
H03D13/00; H03K5/26; G01R25/00; (IPC1-7): H03K5/26; G01R25/00
Domestic Patent References:
JP6058609B2
JP5737252B2
Attorney, Agent or Firm:
Aoki Akira (2 outside)