Title:
【発明の名称】ディジタル信号の伝送方法及び装置
Document Type and Number:
Japanese Patent JP2620477
Kind Code:
B2
Abstract:
PCT No. PCT/DE92/00023 Sec. 371 Date Jul. 19, 1993 Sec. 102(e) Date Jul. 19, 1993 PCT Filed Jan. 16, 1992 PCT Pub. No. WO92/13405 PCT Pub. Date Aug. 6, 1992.During the transmission of digital signals which are interlaced in a multiplex signal, plesiochronic clock frequencies are also matched by means of positive-zero-negative stuffing. In this case, the time intervals of the phase changes can be large in comparison with the time constant of a phase low-pass filter which is formed by a phase-locked loop at the receiving end, which results in a jitter of approximately 1 UI. This jitter can be reduced if additional stuffing processes are inserted in pairs, in such a manner that an additional positive stuffing process (PST) is followed by such a negative stuffing process (NST) or, overall, vice versa, and if the time intervals within the pairs and/or between the pairs are selected in such a manner that the mean value of the phase difference between an incoming digital signal at the transmission end and an outgoing digital signal at the transmission end, which is contained in the multiplex signal, averaged over a specific time duration, remains approximately constant.
Inventors:
Voreynik, Wilhelm
Application Number:
JP50300192A
Publication Date:
June 11, 1997
Filing Date:
January 16, 1992
Export Citation:
Assignee:
Siemens Aktiengesellschaft
International Classes:
H04J3/07; H04L5/22; H04L7/00; (IPC1-7): H04L7/00; H04J3/07
Domestic Patent References:
| JP62291230A | ||||
| JP62202623A |
Other References:
【文献】米国特許4811340(US,A)
【文献】欧州公開248551(EP,A2)
【文献】欧州公開248551(EP,A2)
Attorney, Agent or Firm:
Toshio Yano (2 outside)