Title:
【発明の名称】積層半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2631665
Kind Code:
B2
Abstract:
PURPOSE:To reduce malfunctions at the time of reflow adhering, to reduce punch forming metal molds and to improve production efficiency by connecting corresponding lead terminals of a plurality of IC chips before the chips are isolated from a film tape at the time of mounting them in multi-stage. CONSTITUTION:Film tapes 6, 6 for placing memory ICs 15 are disposed at a predetermined interval in upper and lower stages, corresponding lead terminals 5 are adhered in a state that the ICs 15 are disposed on the tapes 6, 6, the two ICs 15 are simultaneously fed, and mounted on a printed substrate. Since the lead terminals are punch-formed to the 2 ICs 15 with the corresponding terminals 5 adhered, the thickness of the terminals 5 become thick so that its bent scarcely occur advantageously. The type of metal mold may be only one, and since the terminals 5 are adhered in advance even when substrate terminals 11 are adhered to the terminals 5 by reflowing, a malfunction scarcely occur.
Inventors:
ARAKAWA RYUTARO
Application Number:
JP23918087A
Publication Date:
July 16, 1997
Filing Date:
September 24, 1987
Export Citation:
Assignee:
HITACHI MAKUSERU KK
International Classes:
H05K1/18; H01L25/10; H01L25/11; H01L25/18; H05K3/34; (IPC1-7): H01L25/065; H01L21/60; H01L25/07; H01L25/18
Domestic Patent References:
| JP5662351A |
Attorney, Agent or Firm:
Kajiyama Bozen (1 person outside)