Title:
【発明の名称】デジタル位相差検出回路及び位相差検出方法
Document Type and Number:
Japanese Patent JP2642421
Kind Code:
B2
Abstract:
In an apparatus for detecting a phase difference between two digital signals including an n stage delay circuit, an n bit register connected to the n stage delay circuit, a signal encoding means connected to the n bit register, and a compensation circuit connected to the encoder, a test signal is applied to the delay circuit first and two different delayed data are obtained by applying a reference signal to the n bit register twice, the delay characteristics of the delay circuit is calculated by using two different data and the period time of the two reference signals, then a signal to be subjected to phase difference detection is applied to the delay circuit to obtain delayed data by applying a reference signal to the n bit register, the delayed data is compensated at the compensating circuit by using the delay characteristics of the delay circuit. Thus, an accurate phase difference between two digital signals is obtained.
Inventors:
KOBYAMA KYOYUKI
TAKAHASHI HIDENAGA
TAKAHASHI HIDENAGA
Application Number:
JP16209488A
Publication Date:
August 20, 1997
Filing Date:
June 28, 1988
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H03K5/26; G01R25/00; H03D13/00; H03L7/085; H04L7/033; (IPC1-7): H03K5/26; H03D13/00; H03L7/085
Domestic Patent References:
| JP63169143A | ||||
| JP1188048A |
Attorney, Agent or Firm:
Keizo Okamoto