Title:
【発明の名称】集積回路試験装置
Document Type and Number:
Japanese Patent JP2655793
Kind Code:
B2
Abstract:
A method and apparatus for testing a semiconductor integrated circuit device is described. During an aging test of the integrated circuit device, a situation, in which latch up of the semiconductor integrated circuit device can occur, is intermittently created by intermittently supplying a pulse of a power supply voltage Vb, which is higher than a normal voltage Va in accordance with a rated power supply voltage of the tested integrated circuit device. The power supply to the tested semiconductor integrated circuit device is temporarily cut off when latch up occurs. If a second latch up occurs after a restart of the aging test, it is determined that there is an abnormality in the tested semiconductor integrated circuit device. The power supply to the tested semiconductor integrated circuit device is permanently cut off in response to this determination. This prevents damage to the test-object integrated semiconductor device and permits later determination of the degree to which the device is latch up immune.
Inventors:
YOSHINO KENJI
Application Number:
JP34235192A
Publication Date:
September 24, 1997
Filing Date:
December 22, 1992
Export Citation:
Assignee:
KAWASAKI SEITETSU KK
International Classes:
G01R31/30; H01L21/66; G01R31/26; (IPC1-7): G01R31/26; H01L21/66
Attorney, Agent or Firm:
Satoshi Takaya (2 outside)