Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2670288
Kind Code:
B2
Abstract:
PURPOSE:To eliminate an improper short-circuit between lower electrodes, to round corners, and to improve the reliability and yield of a dynamic RAM by depositing a silicon layer by using a selective vapor growth method through a contact hole, and using it as the lower electrode. CONSTITUTION:A silicon substrate 101 having approx. 5-500OMEGAcm of P-type specific resistance (100) is prepared. An oxide film 102 for isolating between elements, a gate oxide film 103, a gate electrode 104, a source/drain diffused layer 105, an interlayer film 106, and a contact hole 107 are sequentially formed. Then, a silicon layer 108 is selectively deposited from the hole 107 by a selective vapor growth method, thereby forming a lower electrode 108. A capacitor insulating film 109, an upper electrode 110, an interlayer insulating film 111, wirings 112 are sequentially formed to form a memory cell. The process of polycrystalline silicon using RIE is eliminated, and a short-circuit between the lover electrodes due to the remaining silicon at the step is obviated. Abrupt corners are removed, and corners are rounded. Thus, the breakdown strength of a capacitor insulating film can be improved.
Inventors:
Kurosawa Kei
Shuichi Samata
Shuichi Samata
Application Number:
JP6814788A
Publication Date:
October 29, 1997
Filing Date:
March 24, 1988
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/04; H01L21/822; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): H01L27/04; H01L21/822; H01L21/8242; H01L27/108
Domestic Patent References:
| JP63226955A |
Attorney, Agent or Firm:
Hideaki Tokawa (1 outside)