Title:
【発明の名称】直交変換装置
Document Type and Number:
Japanese Patent JP2677969
Kind Code:
B2
Abstract:
The output of a butterfly unit is entered into a product-sum unit in a forward DCT and the output of the product-sum unit is entered into the butterfly unit in an inverse DCT. The product-sum unit employs, as a bit-string distribution circuit, a register circuit having eight bit shift registers each having a 16-bit parallel input and a 2-bit shift output and the bit shift registers are different in bit width from one another. Data are entered into the bit shift registers with the largest bit-width bit shift register first, such that the respective bit shift registers are shifted rightward by 2 bits per cycle. Four shift registers are disposed between the bit-string distribution circuit and a RAG circuit such that, when bit strings are entered, as delayed cycle by cycle, into eight RAGs of the RAC circuit, the final accumulation results are successively provided from the RACs in a proper order. This reduces the bi-directional DCT processor in circuit arrangement.
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Inventors:
Kiyoshi Okamoto
Yoshifumi Matsumoto
Toyokura Maki
Yoshifumi Matsumoto
Toyokura Maki
Application Number:
JP30724494A
Publication Date:
November 17, 1997
Filing Date:
December 12, 1994
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/14; G10L25/00; G06T1/20; G10L25/18; H03M7/30; H04N1/41; H04N19/42; H04N19/423; H04N19/436; H04N19/60; H04N19/625; H04N19/85; (IPC1-7): G06F17/14
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)