Title:
【発明の名称】集積回路
Document Type and Number:
Japanese Patent JP2684806
Kind Code:
B2
Abstract:
An integrated circuit comprises a first clock driver responsive to an external clock signal and producing a first clock signal, a second clock driver responsive to the first clock signal and producing a second clock signal delayed from the first clock signal, an internal circuit responsive to the second clock signal and producing an output data signal, and an output circuit coupled to a data output pin and transferring the output data signal to the data output pin in synchronization with the first clock signal, so that a time interval between the production of the output data signal and the validity at the data output pin is shrunk even though a large parasitic capacitance is coupled to the data output pin.
Inventors:
Toshiki Iwata
Application Number:
JP2350890A
Publication Date:
December 03, 1997
Filing Date:
January 31, 1990
Export Citation:
Assignee:
NEC
International Classes:
G06F1/10; G06F1/12; G11C11/407; G11C11/4076; G11C11/409; G11C11/4093; H01L21/822; H01L27/04; H03K5/13; H03K5/133; H03K19/0175; H03L7/00; (IPC1-7): G06F1/10; G06F1/12; H01L21/822; H01L27/04; H03K5/13; H03K19/0175
Domestic Patent References:
| JP61139139A | ||||
| JP6180287A | ||||
| JP3217919A | ||||
| JP2244656A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)