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Title:
【発明の名称】データ伝達回路
Document Type and Number:
Japanese Patent JP2689566
Kind Code:
B2
Abstract:
PURPOSE:To prevent malfunction of the title circuit even when a period for refreshing a data is long or a threshold level of a feedback transistor(TR) is small by using a source voltage of the said TR as a voltage with a lower level than a power voltage when the feedback TR compensating a level notch is turned off. CONSTITUTION:The title circuit is provided with a transfer gate 1, an inverter 2, a 4th TR Q4 of opposite conduction type and a voltage switching section 3. A power voltage VDD is supplied to a source of the 4th TR Q4 in the voltage switching section 3 when a P-channel TR Q6 is turned on with a low level output data OUT and a low level voltage VDD-VT5 (VT5 is a threshold level of TR Q5) is supplied when the output data OUT is at a high level and an N-channel TR Q5 is turned on. Thus, the TR Q4 is not turned on before the output data level is dropped larger than a level VT5+VTP (VTP, is a threshold level of TR Q4)and no malfunction takes place.

Inventors:
Toshiyuki Takeda
Satoru Higashijima
Application Number:
JP1670689A
Publication Date:
December 10, 1997
Filing Date:
January 25, 1989
Export Citation:
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Assignee:
NEC
International Classes:
H03K17/687; H03K3/356; H03K17/06; H03K19/096; (IPC1-7): H03K17/687; H03K3/356; H03K17/06
Domestic Patent References:
JP553234A
JP61161826A
JP60150314A
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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