Title:
【発明の名称】MOS型半導体装置
Document Type and Number:
Japanese Patent JP2695881
Kind Code:
B2
Abstract:
PURPOSE:To decrease power consumption in a fine MOS element and enhance the reliability of it by setting the film thickness of a gate insulation film and the concentration of an impurity of an impurity diffusion layer so that they satisfy a specific condition. CONSTITUTION:A gate electrode 15 is formed on a p-type Si substrate 11 via a gate insulating film 14. Drain and source diffusion layers 12, 13 are formed in such a manner as to overlap a part of the electrode 15. In this construction, the film thickness of a film 14 and the concentration of the impurity of the layers 12, 13 are set so that leak I expressed by a equation resulting from the tunneling among bands in a deep depletion state in the layer 12, 13 at operating time becomes below a permissible leak current. In the equation, integral ds is a surface integration of the area where the electrode 14 and the layers 12, 13 overlap each other viewed from the vertical direction, e is quantity of electron charges, P(E) is a tunnel probability which is a function of electric field E, E1 is an electric field in the interface of the film 14 in the layers 12, 13, E2 is an electric field of a point where the valence bands and the conductance bands have the same potential energy, Es is the permittivity of a semiconductor, and N0 is the concentration of an impurity.
Inventors:
Tetsuro Endo
Riichiro Shirata
Riichiro Shirata
Application Number:
JP31129388A
Publication Date:
January 14, 1998
Filing Date:
December 09, 1988
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L21/8247; H01L21/8242; H01L21/8246; H01L27/10; H01L27/108; H01L27/112; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): H01L29/78; H01L21/8242; H01L21/8247; H01L27/108; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Takehiko Suzue (2 outside)