Title:
【発明の名称】パケットスイッチ
Document Type and Number:
Japanese Patent JP2697477
Kind Code:
B2
Abstract:
PURPOSE:To efficiently test each packet switch in a switch network which is extended in switch scale by connecting packet switches in many stages. CONSTITUTION:Address filter circuits 102 and 103 which check address information of input packets multiplexed on a time-division multiplex bus 101 and pass only packets having corresponding addresses and multiplexing order filter circuits 106 and 107 which pass only packets having the same port number with an input port according to the time-division order are arranged in parallel; and only one side is selected. Therefore, when packet switches are connected in many stages, a through function is used as to all switches other than the test switch to improve the test efficiency.
Inventors:
Hiroshi Nagano
Application Number:
JP11296392A
Publication Date:
January 14, 1998
Filing Date:
May 06, 1992
Export Citation:
Assignee:
NEC
International Classes:
H04Q3/52; H04L12/28; H04L49/111; H04Q11/04; (IPC1-7): H04L12/56; H04L12/28; H04Q11/04
Domestic Patent References:
| JP2218239A | ||||
| JP4105443A | ||||
| JP3270434A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)