Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP2702999
Kind Code:
B2
Abstract:
PURPOSE:To provide an SRAM with a reduced desered area, high resistance to soft error, low power consumption in waiting, and stable operation by locating a gate electrode of a load MOS transistor between a gate electode of a driver MOS transistor and a layer including source and drain areas of the load MOS transistor. CONSTITUTION:A static random access memory cell comprises a complete CMOS type flip-flop circuit including a first conductivity type MOS transistor formed on the surfaces of semicondcutor substrates 1, 2, and a second conductivity type MOS transistor composed of first and second conductor films 8a, 8b, 10a-10c formed on a first insulating film 7 on said MOS transistor and of a second insulating film 9. In said memory cell, gate electrodes 8a, 8b of the second conductivity type MOS transistor are located between gate electrodes 6a, 6c of said first conductivity type MOS transistor and layers 10a-10e including at lesast source and drain areas of said second conductivity type MOS transistor.
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Inventors:
Toshiaki Yamanaka
Yoshio Sakai
Koji Hashimoto
Naotaka Hashimoto
Koichiro Ishibashi
Shimohito Katsuhiro
Takeda Eiji
Yoshio Sakai
Koji Hashimoto
Naotaka Hashimoto
Koichiro Ishibashi
Shimohito Katsuhiro
Takeda Eiji
Application Number:
JP28767488A
Publication Date:
January 26, 1998
Filing Date:
November 16, 1988
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L27/11; H01L21/8244; (IPC1-7): H01L21/8244; H01L27/11
Domestic Patent References:
| JP5892253A | ||||
| JP6319847A | ||||
| JP60246670A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)