Title:
【発明の名称】MOS型半導体装置の製造方法
Document Type and Number:
Japanese Patent JP2712230
Kind Code:
B2
Abstract:
PURPOSE:To install actually a lightly doped drain(LDD) structure and realize isolation of the first and second electrodes with certainty, by providing side walls consisting of insulation substances at side wall parts of the first gate electrode. CONSTITUTION:After forming the first silicon oxide film 101 as the first gate oxide film on a silicon substrate 100, the first polycrystal silicon layer 102 is deposited as the gate electrode material with a CVD technique. Then, ionized phosphorus is implanted and the second silicon oxide film 103 is deposited. After that, the desired patterning is performed so as to etch the above silicon film and the side walls 105 of the third silicon oxide film layer is formed at the side wall parts of the first polycrystal silicon layer 102 as well as the second silicon oxide film 103. After depositing the fourth silicon oxide film 107 as the second gate oxide film and the second polycrystal silicon layer 108 as the second gate electrode material, ion implantation is carried out. As a LDD structure is thus adopted in the production of MOS transistors, stable element characteristics are actualized even though a gate is 0.5mum in length.
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Inventors:
Kazuo Tanaka
Application Number:
JP3329388A
Publication Date:
February 10, 1998
Filing Date:
February 16, 1988
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L29/78; H01L21/336; H01L21/8246; H01L27/10; H01L27/112; (IPC1-7): H01L29/78; H01L21/336
Domestic Patent References:
| JP56133868A |
Attorney, Agent or Firm:
Kisaburo Suzuki (2 outside)