Title:
【発明の名称】電気的消去可能でプログラム可能なリードオンリメモリとその製造方法
Document Type and Number:
Japanese Patent JP2731128
Kind Code:
B2
Abstract:
An electrically erasable and programmable read only memory device includes a first select device and a NAND cell string consisting of a plurality or memory transistors. Each memory transistor has a floating gate separated by a tunnel oxide layer from a channel region formed on a semiconductor substrate and a control gate separated by an interlayer insulation layer from the floating gate. Respective channels of the memory transistors are serially connected to each other by source-drain regions. The control gate is connected to a corresponding word line. The first select device connects one terminal of the NAND cell string to a corresponding bit line. A resistor having a preset resistance value is connected between the first select device and a bit line. An amplifying device amplifies current flowing through the NAND cell string and supplies the amplified current to the bit line.
Inventors:
SAI TEIKAKU
Application Number:
JP10771395A
Publication Date:
March 25, 1998
Filing Date:
May 02, 1995
Export Citation:
Assignee:
SANSEI DENSHI KK
International Classes:
G11C17/00; G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2209774A | ||||
| JP5974666A |
Attorney, Agent or Firm:
Takeshi Takatsuki