Title:
【発明の名称】半導体装置とその製造方法
Document Type and Number:
Japanese Patent JP2740808
Kind Code:
B2
Abstract:
PURPOSE:To avoid the deterioration of device characteristics by connecting a first conductor layer like a cell plate formed through a first insulating film in a groove and on a periphery formed on a substrate to a second conductor layer buried by flattening to the surface of the substrate through a second insulating film in the groove by a third conductor layer made of an electrode material, such as polycrystalline silicon or the like. CONSTITUTION:A groove 2 is formed by anisotropically etching on a semiconductor substrate 1, an oxide film 6 is formed by a CVD method or a heat treating method or the like, a cell plate 7 is formed, for example, by a CVD method, an oxide film 9 is then formed by a CVD method or the like, a polycrystalline silicon is formed by a CVD method as a second diffused layer 5 for burying, then flattened by etching back using anisotropically etching, the film 4 is removed by anisotropically or isotropically etching, an electrode material 10 is then deposited by a CVD method or the like, patterned by a photocomposing step, and a gate insulating film, gate electrode wirings are then deposited by a CVD method or the like.
Inventors:
Toshiaki Ogawa
Ikuo Ogawa
Teruo Shibano
Masao Nagatomo
Koki Okumura
Shunji Katayama
Ohno Kichiwa
Hiroyuki Morita
Ikuo Ogawa
Teruo Shibano
Masao Nagatomo
Koki Okumura
Shunji Katayama
Ohno Kichiwa
Hiroyuki Morita
Application Number:
JP16434987A
Publication Date:
April 15, 1998
Filing Date:
June 30, 1987
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L27/10; H01L21/76; H01L21/822; H01L21/8242; H01L27/04; H01L27/108; (IPC1-7): H01L21/76; H01L21/822; H01L21/8242; H01L27/04; H01L27/108
Domestic Patent References:
| JP634664A | ||||
| JP61244043A | ||||
| JP62101034A | ||||
| JP6242432A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)