Title:
【発明の名称】半導体集積回路装置の製造方法
Document Type and Number:
Japanese Patent JP2749072
Kind Code:
B2
Abstract:
PURPOSE:To obtain a pattern of high resolution by forming a memory cell array region having a high height from a semiconductor substrate surface in the recess of a single crystalline semiconductor substrate and a peripheral circuit region having a low height from a semiconductor substrate surface on the other part. CONSTITUTION:A dynamic random access memory DRAM is composed of a P<-> type semiconductor substrate 1 having a recess on a region formed with a memory cell M. P-type well regions 2 are provided on the memory cell array M forming region of the substrate 1 and the main face of an N-channel MISFETQn forming region, and an N-type well region 3 is provided on the main face of the P-channel MISFET forming region Qp of the substrate 1 for forming a peripheral circuit. A memory cell array region having a high height from the surface of the substrate 1 is formed in the recess of the substrate 1, and a peripheral circuit region having a low height from the surface of the substrate 1 is formed on the other part. Accordingly, an altitude difference between the high region and the low region is reduced, and a pattern image can be analyzed in an exposure having a shallow focal depth. Thus, the pattern having high resolution is obtained.
Inventors:
MORIUCHI NOBORU
YAMAGUCHI YOSHIKI
TANAKA TOSHIHIKO
HASEGAWA NORIO
KAWAMOTO YOSHIFUMI
KIMURA SHINICHIRO
KAGA TOORU
KURE TOKUO
YAMAGUCHI YOSHIKI
TANAKA TOSHIHIKO
HASEGAWA NORIO
KAWAMOTO YOSHIFUMI
KIMURA SHINICHIRO
KAGA TOORU
KURE TOKUO
Application Number:
JP19985688A
Publication Date:
May 13, 1998
Filing Date:
August 12, 1988
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
H01L27/10; H01L21/76; H01L21/8242; H01L27/108; H01L27/105; (IPC1-7): H01L27/108; H01L21/8242
Domestic Patent References:
| JP62165329A | ||||
| JP5955062A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)