Title:
【発明の名称】半導体回路
Document Type and Number:
Japanese Patent JP2753266
Kind Code:
B2
Abstract:
A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.
Inventors:
KODERA NOBUO
YAMASHITA KIICHI
TANAKA HIRONORI
TANAKA SATOSHI
HATSUTA YASUSHI
NAGATA MINORU
YAMASHITA KIICHI
TANAKA HIRONORI
TANAKA SATOSHI
HATSUTA YASUSHI
NAGATA MINORU
Application Number:
JP15028288A
Publication Date:
May 18, 1998
Filing Date:
June 20, 1988
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
International Classes:
G05F3/26; H03F3/34; G05F3/24; H03F3/343; H03F3/347; H03K17/14; (IPC1-7): H03F3/343; G05F3/26
Domestic Patent References:
| JP6257304A |
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)