Title:
【発明の名称】仮想記憶アドレス空間アクセス制御方式
Document Type and Number:
Japanese Patent JP2768503
Kind Code:
B2
Abstract:
A virtual storage address space access control system has an access register(3) having a plurality of access register numbers, a dynamic address translation unit (11) and a translation lookaside buffer (1a) for translating a virtual address to a real address by using a segment table designation. The system further comprises respective first and second control registers (7, 8) for designating a primary and secondary space respectively, the primary and secondary spaces being accessed according to whether the content (access list entry table, ALET) of the access register (3) is "1" or "0"; an access register translation lookaside buffer (6) for indirectly obtaining a segment table designation by using a content of the access register; and an access register auxiliary translation lookaside buffer (4) for directly obtaining the segment table designation by using the access register number. Such an access control system can be employed in a multi-virtual storage system to perform an address translation from a virtual address to a real address at a desirably high speed.
Inventors:
Aiichiro Inoue
Application Number:
JP19226789A
Publication Date:
June 25, 1998
Filing Date:
July 25, 1989
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06F12/10; (IPC1-7): G06F12/10
Domestic Patent References:
| JP1207856A | ||||
| JP1228038A | ||||
| JP2292648A | ||||
| JP2168332A | ||||
| JP56140576A |
Attorney, Agent or Firm:
Mitsuyoshi Okada (3 outside)