【発明の名称】プロセッサ及びメモリの間のトラフィックの経路指定装置

Title:

【発明の名称】プロセッサ及びメモリの間のトラフィックの経路指定装置

Document Type and Number:

Japanese Patent JP2772343

Kind Code:

B2

Abstract:

A method and apparatus for routing processor-memory data traffic in a shared-memory multiprocessor computer system employs an interconnection network including two buffered multistage switching networks. Each of these networks can be used to route the data from any processing element to any memory element. Depending on the nature of the processor-memory traffic, two distinct routing schemes are used to distribute the traffic among the two networks. The first method distributes the memory accesses evenly among the two networks and maximizes performance when the memory accesses are uniformly distributed among the memory modules. However, when the traffic is highly non-uniform, a second routing method is used to confine the non-uniform part of the traffic to one network and the remaining part to the other network. The routing method is selected based on the prevailing traffic conditions. A distributed feedback mechanism detects the change in traffic conditions and changes the routing method accordingly. A traffic monitoring circuit within each memory module monitors the traffic into the memory module continuously and senses a change in the traffic condition. The condition is conveyed to the processing elements by means of a status flag associated with each response message from the memory module to processing elements. The processing elements respond to a change in traffic condition by switching to the alternate routing method.

Inventors:

SAASHU KYARASANI
ANYUUJAN MANAGURA BAAMA

Application Number:

JP20980191A

Publication Date:

July 02, 1998

Filing Date:

July 27, 1991

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