Title:
【発明の名称】ダイナミックRAMの読み出し回路
Document Type and Number:
Japanese Patent JP2773361
Kind Code:
B2
Abstract:
PURPOSE:To suppress the influence of an interferring noide between bit lines and to eliminate malfunction by connecting first and second semiconductor switches to be controlled by respective signal lines between the first and second bit lines in the pair of the respective bit lines. CONSTITUTION:Each time a power source 5 or an additional capacitor 11 is provided, first and second dummy bit lines 12 and 13 are arranged and capacity between the adjacent bit lines is made same in the plural first and second bit lines. A first signal line 20 and a second signal line 30 control a first semiconductor switch 21 and a second semiconductor switch 31 for respectively equalizing the pair of the bit lines. Thus, the influence of the interferring noise between the bit lines is suppressed and the malfunction can be eliminated.
Inventors:
Hiroyuki Yamauchi
Application Number:
JP5342990A
Publication Date:
July 09, 1998
Filing Date:
March 05, 1990
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G11C11/409; G11C11/401; H01L21/8242; H01L27/10; H01L27/108; (IPC1-7): G11C11/401; H01L21/8242; H01L27/108
Domestic Patent References:
| JP6457493A | ||||
| JP1140496A |
Attorney, Agent or Firm:
Tomoyuki Takimoto