Title:
【発明の名称】基板バイアス発生装置
Document Type and Number:
Japanese Patent JP2786184
Kind Code:
B2
Abstract:
PURPOSE:To bring substrate potential quickly to a fixed value by providing a control means with one control means inhibiting the operation of the control means when a power supply is turned ON. CONSTITUTION:Since a limiting circuit 5 is designed so as to inhibit the operation of a control circuit 3 at all times when a power supply is turned ON, a second substrate bias generating means 2 having large capacitance is operated when the power supply is turned ON. When an input terminal 6 reaches a high level, a transistor 7 is turned ON, a gate for a transistor 10 reaches the high level, thc transistor 10 is turned ON, and an output terminal 11 reaches a low level. Since a capacitor 8 is charged at that time, the gate for the transistor 10 holds the high level even when the input terminal 6 reaches the low level after that, and the output terminal 11 continues to hold the low level.
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Inventors:
IKUSHIMA MASAO
Application Number:
JP28252886A
Publication Date:
August 13, 1998
Filing Date:
November 27, 1986
Export Citation:
Assignee:
MATSUSHITA DENSHI KOGYO KK
International Classes:
H01L27/04; G11C11/407; H01L21/822; H01L21/8242; H01L27/02; H01L27/10; H01L27/108; (IPC1-7): H01L27/04; G11C11/407; H01L21/822; H01L21/8242; H01L27/108
Domestic Patent References:
| JP6195561A | ||||
| JP58119228A |
Attorney, Agent or Firm:
Tomoyuki Takimoto