Title:
【発明の名称】サンプルドデータ回路
Document Type and Number:
Japanese Patent JP2799708
Kind Code:
B2
Abstract:
A sampled data circuit having: two or more serially connected sampled data stages (2) each comprising switching means (6) and storage means (10); and clock means (4) for applying to the switching means of consecutive stages clock signals of respectively first and second phases alternating between first and second levels, characterized in that the clock signals also have a third level intermediate the first and second levels which is occupied simultaneously by the first and second phase clock signals.
Inventors:
Michael john gay
Application Number:
JP6556588A
Publication Date:
September 21, 1998
Filing Date:
March 18, 1988
Export Citation:
Assignee:
Motorola Incorporated
International Classes:
H03H19/00; G11C27/00; H03H15/00; H03K5/01; H03K17/16; (IPC1-7): H03H15/00; G11C27/00
Domestic Patent References:
| JP6295800A | ||||
| JP55163692A | ||||
| JP54149547A |
Attorney, Agent or Firm:
Kugoro Tamamushi