Title:
【発明の名称】試験信号パターンを発生する方法
Document Type and Number:
Japanese Patent JP2813384
Kind Code:
B2
Abstract:
An automatic test pattern generator and process assigns value-strength number to selected nodes representing the electrical characteristic strength of integrated circuits including field effect transistors and the logic state values at those nodes. These value-strength numbers become sensitized to the inputs of the selected node and become propagated to outputs of the selected node for establishing patterns for test signals. The test signals later become used in chip testers for determining good and bad integrated circuit chips. The value-strength numbers also become used in dynamic testing of the integrated circuit nodes by using clock signals of the integrated circuit to establish a transition at a start node of a test path. Within a known clock period later, the transition should become captured at an end node of the test path.
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Inventors:
Theo J Powell
John Eye Hickman
Jerry Jay Crowley
John Eye Hickman
Jerry Jay Crowley
Application Number:
JP25371089A
Publication Date:
October 22, 1998
Filing Date:
September 28, 1989
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G01R31/3183; (IPC1-7): G01R31/3183
Domestic Patent References:
| JP62142283A | ||||
| JP61269083A | ||||
| JP5918744B2 |
Attorney, Agent or Firm:
Akira Asamura (2 outside)