【発明の名称】セルバッファ制御方式

Title:

【発明の名称】セルバッファ制御方式

Document Type and Number:

Japanese Patent JP2814980

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To read data from a top position of a cell normally by resetting an FIFO memory and an up-down counter when a cell pulse signal read from the FIFO memory is not detected at first. SOLUTION: A reset signal generating circuit 34 conducts reset processing of an FIFO memory 1 based on a discrimination result received from a top phase comparator circuit 33. When a phase of a reference phase signal is not in matching with any of phase of cell pulse signals read from the FIFO memory 1, the circuit 34 generates a reset signal RST used to conduct reset processing of the FIFO memory 1 storing ATM cell data and provides an output of the signal RST. An EMPTY flag in the FIFO memory 1 connects to a reset terminal of a cell counter 4 and when cell data to be stored in the FIFO memory 1 through the reset processing are idle and the EMPTY flag is active, the cell counter 4 is reset to initialize the count to '0'.

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Inventors:

Michio Masuda

Application Number:

JP9069996A

Publication Date:

October 27, 1998

Filing Date:

April 12, 1996

Export Citation:

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