Title:
【発明の名称】MOSLSIの消費電力見積方法
Document Type and Number:
Japanese Patent JP2824278
Kind Code:
B2
Abstract:
PURPOSE:To shorten the appointed delivery date while cutting down the cost by a method wherein the changes with time or change numbers of output signal levels in logical blocks is multiplied by the mean power consumption data in specific period of the logical blocks or the power consumption data per output level to count the mean power consumption of the logical blocks. CONSTITUTION:The connection data 14, power consumption data 15, signal data 16 of various MOS logical blocks are stored in a date storage. At this time, when the connection data 14 are stored in an input or output buffer, the changes with time of the input-output signal level are outputted as execution results 17 while a power consumption counter 13 counts the AC mean power consumption per respective gate based on the simulation time and the mean power consumption data in specific period of respective gate. Furthermore, the DC mean power consumption per respective input or output buffer is counted based on the changes with time of the input.output signal level and the simulation time to be totaled for counting the mean power consumption of MOS LSI. Through these procedures, the appointed delivery date can be shortened while cutting down the cost.
Inventors:
Yasuhiro Kawakami
Application Number:
JP14482589A
Publication Date:
November 11, 1998
Filing Date:
June 07, 1989
Export Citation:
Assignee:
富士通株式会社
富士通ヴィエルエスアイ株式会社
富士通ヴィエルエスアイ株式会社
International Classes:
G06F17/50; G01R31/26; H01L21/82; H01L21/822; H01L21/8234; H01L27/04; H01L27/088; H03K19/00; (IPC1-7): H01L21/82
Domestic Patent References:
| JP33348A |
Attorney, Agent or Firm:
Hironobu Onda