Title:
【発明の名称】半導体記憶装置及びその情報書込読出消去方法
Document Type and Number:
Japanese Patent JP2825135
Kind Code:
B2
Abstract:
A memory cell includes a transfer transistor having a gate which is connected to a word line, a first electrode which is connected to a bit line, and a second electrode, and a storage capacitor having a storage electrode which is connected to the second electrode of the transfer transistor, a confronting electrode, and a charge storage layer which is provided between the storage electrode and the confronting electrode. The storage capacitor has a capacitance which changes with a hysteresis curve which is determined by a bias voltage applied across the storage electrode and the confronting electrode, so that the capacitance takes one of two values depending on the bias voltage.
Inventors:
EMA TAIJI
KAJITA TATSUYA
KAJITA TATSUYA
Application Number:
JP5440090A
Publication Date:
November 18, 1998
Filing Date:
March 06, 1990
Export Citation:
Assignee:
FUJITSU KK
International Classes:
G11C11/404; G11C11/405; H01L21/8242; H01L21/8247; H01L27/10; H01L27/105; H01L27/108; H01L27/115; H01L29/423; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; G11C11/404; H01L21/8242; H01L27/108; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
Kitano Yoshito