Title:
【発明の名称】半導体メモリ装置
Document Type and Number:
Japanese Patent JP2830594
Kind Code:
B2
Abstract:
A dynamic random access memory device is responsive to a row address signal (ADDr) and a column address signal (ADDc) supplied in synchronism with a system clock signal (CLK) for providing a data path from a data input/ output port (37/38) and a memory cell selected from the memory cell array (31), and latch circuits (32d/ 32i/ 33c/ 33g) are provided in the addressing section (32) and the data transferring path (33) for temporarily storing address decoded signal and write-in and read-out data bits in response to latch control signals (CTL1/ CTL2/ CTL4/ CTL5) higher in frequency than the system clock signal, thereby controlling the data stream in a pipeline fashion.
More Like This:
Inventors:
FUKUZOKURI YUKIO
Application Number:
JP6779592A
Publication Date:
December 02, 1998
Filing Date:
March 26, 1992
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G11C11/407; G11C7/10; G11C11/4096; G11C11/413; H01L27/10; (IPC1-7): G11C11/407; G11C11/413; H01L27/10
Domestic Patent References:
| JP61148692A | ||||
| JP2235291A | ||||
| JP2166696A | ||||
| JP3105791A | ||||
| JP1204292A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)