Title:
【発明の名称】対象の動作を時系列的に検証するシミュレータのためのバックトラッキング方式及びバックトラッキング方法
Document Type and Number:
Japanese Patent JP2835567
Kind Code:
B2
Abstract:
PURPOSE:To perform the back tracking of a simulation only by storing the information corresponding to the number of clock which is much fewer than all the number of clock of the time section to be simulated, by providing a buffer memory means, a sampling means and a back tracking means. CONSTITUTION:This system is composed of an SFL source file 1, a logical inspection part 3 and a logical systhesis part 5, and the logical inspection part 3 includes an SFL syntax analysis translator 31 and an operation simulator 33. The simulation images at the sampling times at some portions from the start of a simulation to the present time is preserved in a buffer memory means. When a back tracking is performed in this state, the simulation image having the sampling time which is the closest to the time to be returned and is before the time is read from the buffer memory means. By defining this image as the starting point, the simulation is reexecuted toward a back tracking point time.
Inventors:
ARAI MASATO
SHIROMIZU SHIGEAKI
SHIROMIZU SHIGEAKI
Application Number:
JP29284793A
Publication Date:
December 14, 1998
Filing Date:
October 28, 1993
Export Citation:
Assignee:
ENU TEI TEI DEETA KK
International Classes:
G06F17/50; G06F11/28; G06F17/00; G06F19/00; (IPC1-7): G06F17/00
Domestic Patent References:
| JP5134870A | ||||
| JP1270164A |
Attorney, Agent or Firm:
Teruyuki Uemura