Title:
【発明の名称】データ処理装置
Document Type and Number:
Japanese Patent JP2836321
Kind Code:
B2
Abstract:
A data processor capable of controlling memory accessing by the same controls regardless of the bus width to be used. A register is provided for storing data to be inputted and completing a block of data with a size equal to that of the whole bus width of the external data bus when the microprocessor accesses external memory by using only a part of the bus width of an external data bus according to a bus-sizing function. A bus interface is provided for starting memory access by dividing a bus cycle into plural portions according to the bus width and for controlling operation so as to access data equal in size to the case where the whole bus width of the external data bus is used for accessing.
Inventors:
KOBAYASHI SOICHI
SAITO JUICHI
SAITO JUICHI
Application Number:
JP28839491A
Publication Date:
December 14, 1998
Filing Date:
November 05, 1991
Export Citation:
Assignee:
MITSUBISHI DENKI KK
International Classes:
G06F13/36; G06F12/04; G06F12/06; G06F12/08; G06F13/40; (IPC1-7): G06F13/36; G06F12/06
Domestic Patent References:
| JP5955525A | ||||
| JP2187849A |
Attorney, Agent or Firm:
Kaneo Miyata (2 outside)