Title:
【発明の名称】完全統合型キャッシュ・アーキテクチャ
Document Type and Number:
Japanese Patent JP2837804
Kind Code:
B2
Abstract:
An integrated cache architecture that has low power consumption, high noise immunity, and full support of an integrated validity/LRU cache write mode. The cache stores TAG, index and LRU information directly on a master word line, and cache line data on local word lines. The access information is made available early in the cycle, allowing the cache to disable local word lines that are not needed. By laying out the master and local word lines in a metal layer that substantially renders the stored data immune to overlaying noise sources, high frequency interconnections can be made over the cache without disturbing the stored data. The cache includes circuitry for efficiently updating the stored LRU information, such that a combined data validity/full LRU cache update protocol is supported.
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Inventors:
ANDORYUU DEEUISU
DEEUITSUDO UIRUZU MIRUTON
DEEUITSUDO UIRUZU MIRUTON
Application Number:
JP6590594A
Publication Date:
December 16, 1998
Filing Date:
April 04, 1994
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G11C11/41; G06F12/08; G06F12/12; G11C15/04; (IPC1-7): G06F12/08; G06F12/08
Domestic Patent References:
| JP4328656A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)