Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP2840948
Kind Code:
B2
Abstract:
PURPOSE:To make wire bonding of high density possible and contrive the miniaturization of an IC chip by forming a pad only not on the circumstance thereof, but also on the center part thereof and shaping a bonding wire with longer connecting distance into a higher and larger loop than shorter connecting distance one. CONSTITUTION:An IC chip 2 is mounted on a substrate 1 and a plurality of rows of pads 3 are arranged around the chip 2. A plurality of external terminals 4 connected to the pads 3 are formed in the neighborhood of the IC chip 2 of the substrate 1. Further, the longer the distance connected by a bonding wire 6, the higher the bonding wire 6 is; a successively smaller loop shape is made in order of bonding wires 6d, 6c, 6b, 6a and the bonding wires are formed so as not to touch each other. Thereby wire bonding can be made at higher density on the IC chip and the miniaturization of the IC chip can be contrived.
Inventors:
MURAKAMI HIRONORI
Application Number:
JP20724288A
Publication Date:
December 24, 1998
Filing Date:
August 23, 1988
Export Citation:
Assignee:
FUJI ZEROTSUKUSU KK
International Classes:
H01L21/60; (IPC1-7): H01L21/60
Domestic Patent References:
| JP5925238A | ||||
| JP60182756A | ||||
| JP62150831A | ||||
| JP61149415U |
Other References:
鵜澤高吉著「電子部品の自動組立入門」初版第１冊（昭５６−７−３０）日刊工業新聞社 ｐ．８４−８７
Attorney, Agent or Firm:
Kiyotaka Sakamoto (1 outside)