Title:
【発明の名称】疑似乱数パタン発生器
Document Type and Number:
Japanese Patent JP2841882
Kind Code:
B2
Abstract:
An artificial random-number pattern generating circuit has a plurality of flip-flops (11-14; 11-15) each having a set signal input terminal and a clock signal input terminal; a plurality of selectors (21-23,25,27; 21-24,26,28) each of which forwards its output to the corresponding flip-flop and receives a first operation mode signal (C1) and/or a second operation mode signal (C2); and an exclusive logical OR gate (30). The artificial random-number pattern generating circuit functions in three different ways, that is as an artificial random-number pattern generator, a boundary scanning buffer or an input buffer. In accordance with the combinations of the first and second operation mode signals. The circuit can make not only a diagnosis of failure in the internal circuit of the LSI but also overall tests including those for input and output buffer circuits of the mounted LSI chip on a board or those for external wirings for the LSI.
Inventors:
OOKUBO CHE
HAGIWARA YASUHIKO
HAGIWARA YASUHIKO
Application Number:
JP1337291A
Publication Date:
December 24, 1998
Filing Date:
February 04, 1991
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R31/317; G01R31/3181; G01R31/3183; G06F7/58; G06F11/27; (IPC1-7): G06F7/58
Domestic Patent References:
| JP62190529A | ||||
| JP6367628A | ||||
| JP63204325A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)